The saga continues

//http://www.mercurynews.com/business/ci_5500085

The last VSA100 silicon on rev A cards would have run 183 just fine.

Rev 2 silicon was broken and you could see screen corruption at 183, that was caused by the display FIFO. We have included a turbo bit to raise the core voltage to 3.0V, but that was never used. 3.0V would get the corruption fixed, but the life span of the parts would be shorter.

The other error we made is to think that the instability was caused by memory. It was not! The board layout killed the internal PCI bus and a little bit more noise on the planes caused the chip 4 to get wrong data.

With proper fixes the card would have gone out at 183. The currect rev A cards with PCI rework will do 183 even with -6 memory. I have margined some rev As at 191 to 195. If you do overclock, please, keep the bambino cool :-P

Hank

AGP VDDQ pins supply voltage to the AGP IO pins. When the card is inserted and power is applied, mother board and the GFX card auto negotiate for the right voltage to be applied to the North Bridge IO and the GFX IO.

If one side is running 1.5V and the other is set to 3.3V you can create a very smelly problem. 3.3V system signals will overdrive the 1.5V system and the protection diodes, tied to 1.5V system at every IO cell, will start dumping all the extra energy to 1.5V rail. TYPEDET# pin informs the system about the voltage to use. 4X AGP cards tie the pin low, 2x and 1x AGP cards leave the pin open.

IF 1.5V rail IO is talking to 3.3V IO the voltage swing is not sufficient to cross the thresh-hold on the 3.3V IO and high level will not be recognized.

3.3V thresh-hold for VSA 100 IO is set to 1/2 VDDQ. 1.5V system required thresh-hold a little higher then 1/2 VDDQ, so another pin was added to provide the reference value to VSA 100 IO cells. Comparator anlong with TYPEDET# value (high or low) will select the proper voltage reference. Voltage reference is a resistor divider, tied between VDDQ and GND, with capacitor bypass to GND to reject high frequency noise.

Another reason, why a separate voltage plane is required for IO is signal path return. The return current on the high speed trace runs directly under the trace to the driving output cell. It will run on GND plane or VDDQ plane. If you provide a separate IO power, the return current has to find another path to the out put cell, that breaks the impedance of the trace and distorts the signal. The return current has to find a capacitor to GND plane, but if the place is not right next to the high speed trace it will break the impedance, whigh would be set to about 68 ohms by trace dimesion and plane separation.

Welcome to the wanderfull world of Signal Integrity (SI).

Hank

In theory this will work for AGP V5 5500 and V4 boards. VSA 100 VDDQ can be set to 1.5V.

Do not try this with V5 6000 the hint bridge will burn up. This also will damage boards, if some yahoos improperly designed V4 boards with VDDQ and 3.3V planes shorted.  I think Powercolor was one of the outfits that did this.

VSA100 has 2 voltage references for 3.3V and 1.5V system. The comparator in the parts autodetects the VDDQ level and switches between the pins. On V5 the references were shorted together, I'll check on this, since I have one card taken appart with chips off. The design files were lost for a very long time.

In theory it might be possible to just cut out the 1.5V key, on V5 5500, and modify the card to take 1.5V directly. I'll have to check it again on the board.

Hank

Bugs, you lost me there.

Why? there is nothing wrong with his posts!

Hank

The standard over-clocker does not work on V5. Only the master chip is programmed to higher clock rates. KoolSmoky did a patch a loooooong time ago to program both chips to higher clock. I just do not remember where he posted it.

If the slave chip is still running at 166 you will not get a boost in performance. Also see that you are in Fastest Performance mode, like mentioned by ahavasi.

Hank

VSA100 never had support for DDR. The signals required for DDR do not exist on the silicon.

Hank

Confirmed, it is not the mother board, The Hint Bridge fried.

I am waiting for a couple of bridges, for repair. This might be the first V5 6000 card with PLX marked bridge .

Hank

I have plenty of Avid fans, just unscrew the old one and put a new one on. Where are you located?

Hank

@roflkopp

I sent you an email last week, did you get it?

Hank

Peltier I used before drew about 2A from 12V, by itself. It will add another 24W to the total system. So you have to remove the heat generated by VSA100 and Peltier device. Passive cooling will not do.

Hank

Sure, give it a try. Let me know how it goes.

Hank

Looks like you will have to send it back to 6000 garage. You pay for shipping.

Hank

Command FIFO is in the Frame Buffer memory, if you get a single bit error in the command FIFO region, you will lock up.

Both chips have a lower 1MB of Frame Buffer memory reserved for command FIFO. The FIFOs in both chips have identical command information. If one chip stalls (locks) both will stop and machine will freeze.

Hank

3DFX.com still belongs to   NVIDIA US INVESTMENT COMPANY  
until 05/02/2008

The server might have been taken down though.

Hank