Da PCI-SIG, l'organizzazione responsabile della definizione degli standard che guidano l'evoluzione della tecnologia PCI-Express, ha reso noto, mediante il comunicato stampa allegato di seguito, di aver definito le specifiche del PCI-Express di nuova generazione. A valle di un periodo durato 60 giorni, nei quali č stata analizzata la revisione 0.9 del PCI-E 2.0, PCI-SIG ha infatti approvato le specifiche di base del PCI-Express 2.0.
Tra le principali innovazioni che la nuova tecnologia introdurrą segnaliamo l'incremento del data rate che con il suo valore nominale di 5GT/s promette prestazioni doppie rispetto all'attuale versione 1.1 del PCI-E. Le 16 linee di un bus PCI-E 2.0 sono inoltre in grado di assicurare una banda massima di 16Gb/S mentre agli sviluppatori viene offerta la possibilitą di modulare la velocitą puntuale di ciascuna linea.
BEAVERTON, Ore. - January 15, 2007 - PCI-SIG, the Special Interest Group responsible for PCI Express industry-standard I/O technology, today announced the availability of the PCI Express Base 2.0 specification. After a 60-day review of revision 0.9 of the specification in Fall 2006, members of the PCI-SIG finalized and released PCI Express (PCIe) 2.0, which doubles the interconnect bit rate from 2.5GT/s to 5GT/s to support high-bandwidth applications.
The specification seamlessly extends the data rate to 5GT/s in a manner compatible with all existing PCIe 1.1 products currently supporting 2.5GT/s signaling. The key benefit of PCIe 2.0 is its faster signaling, effectively increasing the aggregate bandwidth of a 16-lane link to approximately 16 GB/s. The higher bandwidth will allow product designers to implement narrower interconnect links to achieve high performance while reducing cost.
"In today's world, applications are becoming more advanced and are requiring more bandwidth," said Al Yanes, PCI-SIG chairman and president. "This is the perfect time to release PCIe 2.0, which not only supports high-bandwidth applications such as high-end graphics, but also adds many new architectural enhancements."
In addition to the faster signaling rate, PCI-SIG working groups also added several new protocol layer improvements to the PCIe Base 2.0 specification which will allow developers to design more intelligent devices to optimize platform performance and power consumption while maintaining interoperability, low cost and fast market introduction. These architecture improvements include:
- Dynamic link speed management allows developers to control the speed at which the link is operating
- Link bandwidth notification alerts platform software (operating system, device drivers, etc) of changes in link speed and width
- Capability structure expansion increases control registers to better manage devices, slots and the interconnect
- Access control services allows for optional controls to manage peer-to-peer transactions
- Completion timeout control allows developers to define a required disable mechanism for transaction timeouts
- Function-level reset provides an optional mechanism to reset functions within a multi-function device
- Power limit redefinition enables slot power limit values to accommodate devices that consume higher power
