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WASHINGTON, D.C. -- December 6, 2005 --In
papers presented at the International Electron Devices Meeting (IEDM)
in Washington, D.C., IBM (NYSE: IBM) and AMD (NYSE: AMD) today detailed
their progress in bringing new, advanced semiconductor process
technologies and materials to the 65 nanometer (nm) technology
generation.
The companies announced that they have successfully combined
embedded Silicon Germanium (e-SiGe) with Dual Stress Liner (DSL) and
Stress Memorization technology (SMT) on Silicon-On-Insulator (SOI)
wafers, resulting in a 40 percent increase in transistor performance
compared to similar chips produced without stress technology, while
controlling power consumption and heat dissipation. The new process
technologies reduce interconnect delay through the use of lower
dielectric constant (lower-K) insulators, which can improve overall
product performance and lower power consumption. In addition, the new
technologies have shown ability to be manufactured at the 65nm
generation and scaleable for use in future generations.
“Our joint work on developing advanced process technologies
continues to ensure we can create and provide the highest performance,
lowest power processors on the market,” said Nick Kepler, vice
president of logic technology development at AMD. “Yet again, we can
add another achievement to our list of successes that demonstrate how
shared expertise and skills can result in overcoming roadblocks and
creating more valuable innovations for customers.”
“At IBM, we strongly believe that our unique joint development
partnership with AMD at East Fishkill, N.Y. is key to overcoming power
and heat challenges as the industry reaches near atomic scales,” said
Gary Patton, vice president, technology development at IBM's
Semiconductor Research and Development Center. “The successful
integration of leadership technologies from IBM, AMD and our partners
at 65nm demonstrates the strength of our collaborative innovation
model.”
Additional details about third generation strain technology
innovations from AMD and IBM will be disclosed at the 2005 IEEE
International Electron Devices Meeting, December 5-7, 2005 in
Washington, D.C. This technology was developed as part of the AMD and
IBM joint development alliance at AMD’s fabrication facilities in
Dresden, Germany, and at the IBM Semiconductor Research and Development
Center in East Fishkill, N.Y.
in Taiwan.
Source: AMD Press Release
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