IBM e Intel Corporation, con il supporto di un ampio numero di aziende del settore, hanno messo a punto una proposta, il cui nome in codice è Geneseo, che mira all'evoluzione della tecnologia PCI-Express al fine di garantire i livelli prestazionali richiesti dalle applicazioni di nuova generazione che verranno sviluppate negli ambiti grafico, finanziario, matematico e in quelli della criptazione e decriptazione dei dati trasmessi attraverso le infrastrutture di rete e della modellazione di modelli matematici complessi.

Il progetto di Intel ed IBM si basa sulla definizione di una nuova architettura in forma di Open Standard che prevede l'utilizzo di componenti, quali co-processori e acceleratori, in aggiunta al design tipico dei sistemi server e consenta così l'incremento delle performance in presenza delle complesse applicazioni in arrivo a medio termine.

Il ventaglio di aziende minori che supportano Geneseo include Adaptec Inc., AGEIA Technologies Inc., Altera Corporation, Broadcom Corporation, Celoxica, Cisco Systems, ClearSpeed Technology, Dell, EMC Corporation, Emulex Corporation, HP, Integrated Device Technology Inc., Lecroy Corporation, Linux Networx, LSI Logic, Mellanox Technologies, Myricom, NetEffect, Novell, NVIDIA, PLX Technology, PMC-Sierra, QLogic, Sun Microsystems, Synopsys, Tektronix, Xambala Inc., Xilinx Inc. e Xtreme Data.

INTEL DEVELOPER FORUM, San Francisco, Sept. 27, 2006 – IBM and Intel Corporation, with support from dozens of other companies, have developed a proposal to enhance PCI Express* technology to address the performance requirements of new usage models, such as visualization and extensible markup language (XML).

The proposal, codenamed “Geneseo,” outlines enhancements that will enable faster connectivity between the processor -- the computer’s brain -- and application accelerators, and improve the range of design options for hardware developers. Applications that will benefit include visualization, such as complex weather modeling; math and physics, such as data intensive financial applications; and content processing, such as the encryption and decryption of communications infrastructure data.

“IBM is co-founding a new open standard for attaching accelerators and co-processors to server platforms,” said Dr. Tom Bradicich, IBM fellow and chief technology officer, System x™ and BladeCenter® Servers. “Like PCI-X, InfiniBand and PCI Express, this new architecture defines a standards-based approach for improving general purpose server accessibility within new and emerging application areas, such as encryption, visualization, XML and complex mathematical modeling.”

“Five years ago Intel, along with IBM and other industry leaders, laid out a 10-year vision for an open, standards-based interface for the entire computer industry,” said Pat Gelsinger, senior vice president, general manager, Intel’s Digital Enterprise Group. “In 2004, PCI Express was the first step and today is the overwhelming choice for desktop, mobile and server systems. Geneseo is the next step in this vision and will address new requirements and opportunities that come with next-generation platforms.”

Geneseo is supported by key technology companies including Adaptec Inc., AGEIA Technologies Inc., Altera Corporation, Broadcom Corporation, Celoxica, Cisco Systems, ClearSpeed Technology, Dell, EMC Corporation, Emulex Corporation, HP, Integrated Device Technology Inc., Lecroy Corporation, Linux Networx, LSI Logic, Mellanox Technologies, Myricom, NetEffect, Novell, NVIDIA, PLX Technology, PMC-Sierra, QLogic, Sun Microsystems, Synopsys, Tektronix, Xambala Inc., Xilinx Inc. and Xtreme Data.

PCI Express technology was first delivered in client and server computing platforms in 2004. Its introduction signaled the transition of computing platform I/O from the parallel bus model that had existed since the PC industry’s inception to a high-speed, serial I/O standard. Since this time, millions of PCI Express-enabled platforms and devices have been delivered to customers, and PCI Express has emerged as the industry’s choice for platform I/O and internal interconnect connectivity.

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